Since the invention of the integrated circuit, the semiconductor industry has experienced a constant rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvement in lithography has resulted in considerable improvement in 2D integrated circuit formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
An additional limit comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit RC delay and power consumption increase.
Three-dimensional (3D) integrated circuits (ICs) are therefore created to resolve the above-discussed limitations. In a typical 3D integrated circuit formation process, two wafers, each including an integrated circuit, are formed. The wafers are then bonded with the devices aligned. Deep vias are then formed to interconnect devices on the first and second substrates.
Much higher device density has been achieved using 3D IC technology, and up to six layers of wafers have been bonded. As a result, the total wire length is significantly reduced. The number of vias is also reduced. Accordingly, 3D technology has the potential of being the mainstream technology of the next generation.
Conventional methods for bonding two wafers include adhesive bonding, direct copper bonding and direct oxide bonding. Adhesive bonding is performed by bonding two wafers with an adhesive. This approach is relatively easy and the cost is low. A main problem of this approach is the low thermal stability and extendibility. When a third wafer is bonded to the two already bonded wafers, the existing adhesive between the first and the second wafers may contract under the thermal conditions, and the potentially uneven contraction generates stresses. Therefore, it is difficult to bond three or more wafers together.
In direct copper bonding, each of the two wafers have copper pads exposed on the surfaces of the wafers, and the two wafers are bonded by applying a high pressure, which is typically about 80 pounds per square inch (psi) to about 100 psi. Under such a high pressure, low-k dielectric materials on the wafers are densified, and the respective k values are increased, undesirably.
In direct oxide bonding, the two wafers have oxide layers on the respective surfaces of the wafers, and are bonded oxide-to-oxide. Vias are then formed through the oxide layers to connect the wafers. Direct oxide bonding typically requires a temperature as high as 900° C., or a temperature of about 400° C. to about 500° C. plus a pressure of about 40 psi to about 50 psi. The high temperature and/or high pressure also cause the k values of the low-k dielectric materials to increase.
The conventional adhesive bonding, direct copper bonding and direct oxide bonding are suitable for forming 3D integrated circuits with relatively high-k dielectric materials, for example, dielectric materials having k values greater than about 3.5. However, these methods either cause an increase in k values of porous low-k materials or have an extendibility problem. As such, the existing technologies are not suitable for 3D integrated circuits with low-k dielectric materials, and thus a novel method is needed.